In power semiconductor devices, MOSFETs play an important role in various power conversions, especially high-frequency power conversions, with high speed, low switching loss, and low driving loss. In the low-voltage field, MOSFET has no competitors, but as the withstand voltage of MOS increases, the on-resistance increases with the power of 2.4-2.6, and its growth rate makes MOSFET manufacturers and users have to reduce it by dozens of times. Rated current to compromise the contradiction between rated current, on-resistance and cost. Even so, the on-voltage drop generated by the on-resistance of the high-voltage MOSFET at the rated junction temperature is still high. The rated junction temperature and rated current of the MOSFET with a withstand voltage of more than 500V have a high on-voltage, with a withstand voltage of 800V. The above turn-on voltage is surprisingly high, and the turn-on loss accounts for 2/3-4/5 of the total MOSFET loss, which greatly limits the application.
1. The principle and method of reducing the on-resistance of high-voltage MOSFET
(1) On-resistance distribution of MOSFETs with different withstand voltages
MOSFETs with different withstand voltages have different resistance ratio distributions in each part of the on-resistance. For example, the epitaxial layer resistance of a MOSFET with a withstand voltage of 30V is only 29% of the total on-resistance, and the epitaxial layer resistance of a MOSFET with a withstand voltage of 600V is 96.5% of the total on-resistance. From this, it can be inferred that the on-resistance of a MOSFET with a withstand voltage of 800V will be almost occupied by the epitaxial layer resistance. To obtain a high blocking voltage, a high resistivity epitaxial layer must be used and thickened. This is the root cause of the high on-resistance caused by conventional high voltage MOSFET structures.
(2) Ideas for reducing the on-resistance of high-voltage MOSFETs
Although increasing the die area can reduce the on-resistance, the cost of increasing the cost is not allowed by commercial products. Although the introduction of minority carrier conduction can reduce the on-state voltage drop, the price paid is the reduction of switching speed and the occurrence of trailing current, the increase of switching loss, and the loss of the high-speed advantage of MOSFET.
The above two methods cannot reduce the on-resistance of the high-voltage MOSFET. The remaining idea is how to separate the low-doping and high-resistivity regions that block high voltage and the high-doping and low resistivity of the conduction channel. For example, there is no other purpose except that the low-doped high-voltage epitaxial layer can only increase the on-resistance when it is turned on. In this way, is it possible to realize the conduction channel with high doping and lower resistivity, and try to pinch off this channel in some way when the MOSFET is turned off, so that the withstand voltage of the whole device depends only on the low doping N-epitaxial Floor. Based on this idea, INFINEON launched COOLMOS with built-in lateral electric field withstand voltage of 600V in 1988, which made this idea come true.
2. The main characteristics of the built-in lateral electric field MOSFET
(1) Reduction of on-resistance
INFINEON's MOSFET with built-in lateral electric field has a withstand voltage of 600V and 800V. Compared with conventional MOSFET devices, with the same die area, the on-resistance is reduced to 1/5 and 1/10 of conventional MOSFETs; the same rated current, The on-resistance drops to 1/2 and about 1/3, respectively. Under the conditions of rated junction temperature and rated current, the turn-on voltage drops from 12.6V and 19.1V to 6.07V and 7.5V respectively; the turn-on loss drops to 1/2 and 1/3 of conventional MOSFETs. Due to the reduction of conduction loss, the heat generation is reduced, and the device is relatively cool, so it is called COOLMOS.
(2) reduction and reduction of thermal resistance
The die of the COOLMOS with the same rated current is reduced to 1/3 and 1/4 compared with the conventional MOSFET, which reduces the package size by two.
Since the thickness of the COOLMOS die is only 1/3 of the conventional MOSFET, the RTHJC of the TO-220 package is reduced from the conventional 1°C/W to 0.6°C/W; the rated power is increased from 125W to 208W, which improves the heat dissipation capability of the die.
(3) Improvement of switching characteristics
The gate charge and switching parameters of COOLMOS are better than that of conventional MOSFET. Obviously, due to the reduction of QG, especially QGD, the switching time of COOLMOS is about 1/2 of that of conventional MOSFET; the switching loss is reduced by about 50%. The decrease in off-time is also related to the low gate resistance (<1Ω=) inside the COOLMOS.
(4) Avalanche breakdown resistance and SCSOA
At present, the new MOSFETs have the ability to resist avalanche breakdown without exception. COOLMOS is also avalanche resistant. Under the same rated current, the IAS of COOLMOS is the same as ID25℃. However, due to the reduced die area, the IAS is smaller than a conventional MOSFET, while with the same die area, both the IAS and the EAS are larger than the conventional MOSFET.
Disclaimer: The content of this article comes from the Internet and is only for learning and communication. All views belong to the original author, which does not mean that they support or agree with the views. If your rights are violated, please contact us to delete in time.
